1. Field
Embodiments of the present disclosure relate to a semiconductor memory device and, more particularly, to a technology for increasing area availability of a memory device in a Peripheral Under Cell (PUC) structure.
2. Description of the Related Art
With advancements in semiconductor technology, the demand for highly-integrated memory devices continues to increase. The conventional method for increasing integration has been to reduce the amount of area each memory cell occupies on the substrate.
However, the conventional method has reached a limit in its physical ability to reduce memory cell size. In order to address this issue, methods for fabricating memory devices having three-dimensionally arranged memory cells have recently been proposed. If the memory cells are arranged in three dimensions, the semiconductor substrate area can be used more efficiently.